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description the ats636lse programmable, true power-on state (tpos), device is optimized hall-effect ic and rare-earth pellet combinations that switch in response to magnetic signals created by ferromagnetic targets in gear-tooth sensing and proximity applications. the device is externally programmable. a wide range of programmability is available on the magnetic operate point (b op ) while the hysteresis remains fixed. this advanced feature allows for optimization of the circuit switchpoint and can drastically reduce the effects of mechanical placement tolerances found in production environments . a proprietary dynamic offset cancellation technique, with an internal high-frequency clock, reduces the residual offset voltage, which is normally caused by device overmolding, temperature dependencies, and thermal stress. having the hall element and amplifier in a single chip minimizes many problems normally associated with low-level analog signals. this device is ideal for use in gathering speed or position information using gear-tooth-based configurations, or for proximity sensing with ferromagnetic targets. 635lse-ds, rev. 5 features and benefits ? chopper stabilization ? extremely low switchpoint drift over temperature ? on-chip protection ? supply transient protection ? output short-circuit protection ? reverse-battery protection ? true zero-speed operation ? true power-on state ? single-chip sensing ic for high reliability ? optimized magnetic circuit ? wide operating voltage range ? internal regulator programmable back biased hall-effect switch with tpos functionality continued on the next page? package: 4-pin sip (suffix se) not to scale ats636lse functional block diagram reg clock/logic amp s/h lpf current limit vcc out gnd programmming logic program / lock offset adjust to all subcircuits
programmable back biased hall-effect switch with tpos functionality 2 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com ats636lse the ats636lse has the opposite polarity and switches low in the presence of a ferromagnetic target or tooth and switches high in the presence of a target valley, window, or when the ferromagnetic target is removed. these devices are lead (pb) free, with 100% matte tin leadframe plating. description (continued) pin-out diagram absolute maximum ratings characteristic symbol notes rating unit supply voltage v cc fault conditions that produce supply voltage transients will be clamped by an internal zener diode. these conditions can be tolerated but should be avoided. 28 v reverse supply voltage v rcc ?18 v overvoltage supply current i cc 100 ma output off voltage v out 26.5 v output sink current i out internal current limiting is intended to protect the device from output short circuits, but is not intended for continuous operation. 20 ma magnetic flux density b unlimited ? package power dissipation p d see graph ? operating ambient temperature t a range l ?40 to 150 oc junction temperature t j 165 oc storage temperature range t stg ?65 to 170 oc terminal list number name function 1 vcc device supply 2 vout device output 3 nc no connect 4 gnd device ground selection guide part number output (tooth) packing * ats636lsetn-t low 13-in. reel, 450 pieces/reel * contact allegro ? for additional packing options. 24 3 1
programmable back biased hall-effect switch with tpos functionality 3 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com ats636lse electrical characteristics over operating voltage and junction temperature range; unless otherwise noted characteristics symbol test conditions min. typ. 1 max. unit supply voltage 2 v cc operating 4.2 ? 24 v power-up state pos after programming v cc = 0 v cc (min), t > t on : b < b op high high high ? low output voltage v out(sat) output on, i out = 20 ma ? 175 400 mv output current limit 3 i outm pulse test method, output on 30 50 90 ma output leakage current i off output off, v out = 24 v ? ? 10 a supply current i cc output off (high) ? 2.5 5.5 ma output on (low) ? 2.5 5.5 ma reverse supply current i rcc v rcc = ?18 v ? ? ?5 ma power-on delay 4 t on output off, v cc > v cc (min) ? 35 50 s output rise time t r r l = 820 , c l = 10 pf ? 1.2 5 s output fall time t f r l = 820 , c l = 10 pf ? 1.2 5 s sampling frequency f sample ? 250 ? khz supply zener voltage v zsupply i cc = i cc (max) + 3 ma, t a = 25c 28 ? ? v output zener voltage v zoutput i out = 3 ma, t a = 25c 30 ? ? v supply zener current 5 i zsupply v s = 28 v ? ? 8.5 ma output zener current i zoutput v o = 30 v ? ? 3 ma 1 typical data is at v cc = 12 v and t a = 25c. 2 do not exceed the maximum thermal junction temperature: see power derating curve. 3 short circuit protection is not intended for continuous operation and is tested using pulses. 4 the power-on delay is the time that is necessary before the output signal is valid. 5 the maximum spec limit for this parameter is equivalent to i cc (max) + 3 ma.
programmable back biased hall-effect switch with tpos functionality 4 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com ats636lse magnetic characteristics over operating voltage and junction temperature range using reference target; unless otherwise noted characteristics symbol test conditions min. typ. max. unit number of programming bits switchpoint ? 7 ? bit switchpoint polarity ? 1 ? bit programming lock ? 1 ? bit gear tooth / proximity characteristics (low switchpoint only) programming air gap range 1 ag range temperature = 25c, code = ?127 2.5 ? ? mm temperature = 25c, code = +127 ? ? 1.5 mm programming resolution ag res temperature = 25c program air gap = 2.5 mm ? 0.05 ? mm air gap drift over full temperature range 2 ag drift device programmed to 2.5 mm ? 0.2 ? mm polarity p over tooth (ats636lse) ? low ? ? over valley (ats636lse) ? high ? ? 1 the switchpoint will vary over temperature. a sufficient margin obtained through customer testing is required to guarantee func tionality over temperature. programming at larger air gaps leaves no safety margin for switchpoint drift. see the applications note proximity sensing programming technique on the allegro website at http://www.allegromicro.com for additional information. 2 the switchpoint will vary over temperature, proportionally to the programmed air gap. this parameter is based on characterizati on data and is not a tested parameter in production. switchpoint air gap generally drifts downward as temperature increases. tooth and valley field vs. air gap reference target 0 200 400 600 800 1000 1200 1400 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 air gap [mm] flux density [gauss] reference target tooth reference target valley reference target tooth and valley field vs. air gap reference target flux density vs. position 0 200 400 600 800 1000 1200 1400 0 30 60 90 120 150 180 210 240 270 300 330 360 position (o) flux density (gauss) 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25 5.50 5.75 6.00 reference target flux density vs. position: typical
programmable back biased hall-effect switch with tpos functionality 5 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com ats636lse characteristic performance i cc on 0 1 2 3 4 5 6 -50 -25 0 25 50 75 100 125 150 175 temperature (c) i cc (ma) 4v 15v 24v i cc off 0 1 2 3 4 5 6 -50 -25 0 2 5 5 0 75 100 125 150 175 temperature (c) i cc (ma) 4v 15v 24v v sat 0 100 200 300 400 500 -50 -25 0 25 50 75 100 125 150 175 temperature (c) v sat (mv) 20ma data taken from 3 lots, 30 pieces/lot reference target 8x
programmable back biased hall-effect switch with tpos functionality 6 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com ats636lse b op /b rp vs. program code 0 1 2 3 4 5 6 7 -50 0 50 100 150 200 temperature (c) air gap (mm) code -8 bop code -8 brp code 0 bop code 0 brp code +32 bop code +32 brp code +127 bop code +127 brp notes: ? air gaps for code 127 at 150c are interpolated due to test limitations at minimum air gap. ? these graphs are intended to provide an understanding of how the program codes affect the switchpoints. in a production environment, individual devices would be programmed to individual codes to ensure all devices switch at the same air gap. data taken from 3 lots, 30 pieces/lot reference target 8x
programmable back biased hall-effect switch with tpos functionality 7 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com ats636lse gear parameters for correct operation characteristic description min. typ. max. unit tooth whole depth (h t ) depth of target valley 5 ? ? mm circular valley length (p c ? t) length of target valley 13 ? ? mm circular tooth length (t) length of target tooth 5 ? ? mm face width (f) thickness or width of target tooth 5 ? ? mm reference target dimensions target outside diameter (d o ) face width (f) circular tooth length (t) circular valley length (p c ? t) tooth whole depth (h t ) reference target 120 mm 6 mm 23.5 mm 23.5 mm 5 mm reference target reference target material: crs 1018 electromagnetic capability (emc) performance please contact allegro microsystems for emc performance test name reference specification esd ? human body model aec-q100-002 esd ? machine model aec-q100-003 conducted transients iso 7637-1 direct rf injection iso 11452-7 bulk current injection iso 11452-4 tem cell iso 11452-3
programmable back biased hall-effect switch with tpos functionality 8 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com ats636lse functional description chopper-stabilized technique the basic hall element is a small sheet of semiconductor material in which a constant bias current will flow when a constant volt- age source is applied. the output will take the form of a voltage measured across the width of the sheet and will have negligible value in the absence of a magnetic field. when a magnetic field with flux lines at right angles to the hall current is applied, a small signal voltage directly proportional to the strength of the magnetic field will occur at the output terminals. this signal voltage is proportionally small relative to the offset produced at the input of the chip. this makes it very difficult to process the signal and maintain an accurate, reliable output over the specified temperature and voltage range. therefore, it is important to reduce any offset on the signal that could be ampli- fied when the signal is processed. chopper stabilization is a unique approach used to minimize input offset on the chip. this technique removes a key source of output drift with temperature and stress, and produces a 3 reduc- tion in offset over other conventional methods. this offset reduction chopping technique is based on a signal modulation-demodulation process. the undesired offset signal is separated from the magnetically induced signal in the frequency domain. the offset (and any low frequency noise) component of the signal can be seen as signal corruption added after the signal modulation process has taken place. therefore, the dc offset is not modulated and remains a low frequency component. con- sequently, the signal demodulation process acts as a modulation process for the offset causing the magnetically induced signal to recover its original spectrum at baseband while the dc offset becomes a high frequency signal. then, using a low pass filter, the signal passes while the modulated dc offset is suppressed. the advantage of this approach is significant offset reduction, which desensitizes the chip against the effects of temperature and stress. the disadvantage is that this technique features a demodu- lator that uses a sample and hold block to store and recover the signal. this sampling process can slightly degrade the signal-to- noise ratio (snr) by producing replicas of the noise spectrum at the baseband. the degradation is a function of the ratio between the white noise spectrum and the sampling frequency. the effect of the degradation of the snr is higher jitter, a.k.a. signal repeat- ability. in comparison to a continuous time device, the jitter spec can be increased by a factor of five. regulator amplifier sample/ hold clock hall element figure 1. concept of chopper-stabilization algorithm
programmable back biased hall-effect switch with tpos functionality 9 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com ats636lse the ats636lse magnetic operate point, b op , is programmed by serially addressing the devices through the supply terminal (1). after the correct operate point is determined, the device program- ming bits are selected and blown, then a lock bit is selected and blown to prevent any further (accidental) programming. addressing b op is programmable in both the positive and negative direction from its initial value. addressing is used to determine the desired code, while programming is used to lock the code. a unique key is needed to blow fuses, while addressing as described below does not allow for the device to be pro- grammed accidentally. addressing with positive polarity the magnetic oper- ate point, b op , is adjustable using 7 bits or 128 addresses. the addresses are sequentially selected (figure 2) until the required operate point is reached. the first address must be selected with a high voltage pulse, v pp , while the remaining pulses should be v ph pulses. note that the difference between b op and the magnetic release point, b rp , the hysteresis, b hys , is fixed for all addresses. addressing with negative polarity the magnetic operate point, b op , is adjustable with negative polarity using 7 bits or 128 addresses. to invert the polarity it is necessary to first apply a keying sequence (figure 3). the polarity key contains a v pp pulse and at least 1 v ph pulse, but no more than 6 v ph pulses; the key in figure 3 shows 2 v ph pulses. the addresses are then sequentially selected until the required operate point is reached. the first address must be selected with a high voltage pulse, v pp , while the remaining pulses should be v ph pulses. 0 v pl v ph t d(1) t d(0) code 1 code 2 code 3 code n-2 code n-1 code n (up to 127) v pp figure 2. addressing pulses: positive p olarity 0 v pp v pl v ph t d(1) t d(0) code -1 code -2 code -3 code -(n-2) code -(n-1) code -n (up to -127) polarity key figure 3. address ing pulses: negative polarity addressing / programming protocol programming protocol valid over operating temperature range, unless otherwise noted characteristics symbol test conditions min. typ. max. units programming protocol (t a = 25c) programming voltage 1,2 v pl minimum voltage range during programming 4.5 5 5.5 v v ph 8.5 ? 15 v v pp 25 ? 27 v programming current i pp maximum supply current during programming ? 500 ? ma pulse width t d(0) off-time between bits 20 ? ? s t d(1) enable, address, program, or lock bit on-time 20 ? ? s t dp program pulse on-time 100 300 ? s pulse rise time t r v pl to v ph or v pp ? ? 11 s pulse fall time t f v ph or v pp to v pl ? ? 5 s 1 programming voltages are measured at pin 1 (vcc) of the sip. a minimum capacitance of 0.1 f must be connected from vcc to gnd of the sip to provide the current necessary to blow the fuse. 2 testing is the only method that guarantees successful programming.
programmable back biased hall-effect switch with tpos functionality 10 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com ats636lse program enable to program the device, a keying sequence is used to activate / enable the programming mode as shown in figure 4. this program key sequence consisting of a vpp pulse, at least seven vph pulses, and a vpp pulse with no supply interrup- tions. the sequence is designed to prevent the device from being programmed accidentally (e.g., as a result of noise on the supply line). code programming after the desired switchpoint code is selected (0 through 127), each bit of the corresponding binary address should be programmed individually, not at the same time. for example, to program code 5 (binary 000101), bits 1 and 3 need to be programmed. a bit is programmed by addressing the code and then applying a v pp pulse, the programming is not reversible. an appropriate sequence for blowing code 5 is shown in figure 5. polarity bit programming if the desired switchpoint has negative polarity, the polarity bit must be programmed. to do this it is necessary to first apply the polarity key sequence before the program key sequence (figure 6). finally a v pp pulse of duration t dp must be applied to program this bit, the programming is not reversible. the polarity bit is for adjusting programming range only and will not affect the output polarity. 0 t d(1) t d(1) t d(0) program enable 7 or more pulses (8 pulses shown) v pl v ph v pp figure 4. program e nable pulse sequence figure 5. code programming example v ph v pp program enable 0 v pl t d(1) t d(1) t d(0) t dp polarity key polarity bit program figure 6. polarit y bit programming v ph v pp program enable bit 1 address bit 1 program bit 3 address 000100 code 4 bit 3 program program enable 0 v pl t d(1) t d(1) t d(0) t dp 000001 code 1
programmable back biased hall-effect switch with tpos functionality 11 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com ats636lse lock-bit programming after the desired code is programmed, the lock bit (code 128), can be programmed (figure 7) to prevent further programming of the device. again, programming is not reversible. see allegro website at http://www.allegromicro.com for extensive information on device programming as well as programming products. programming hardware is available for purchase and programming software is available for free. figure 7. lock -bit programming pulse sequence v ph v pp program enable 0 v pl t d(1) t d(1) t d(0) t dp lock bit address 128 pulses lock bit program
programmable back biased hall-effect switch with tpos functionality 12 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com ats636lse for applications it is strongly recommended that an external ceramic bypass capacitor in the range of 0.01 f to 0.1 f be connected between the supply and ground of the device to reduce both external noise and noise generated by the chopper-stabi- lization technique. (the diagram below shows a 0.1 f bypass capacitor.) the series resistor r s in combination with the bypass capacitor creates a filter for emc pulses. the series resistor will have a drop of approximately 800 mv, this must be considered for the minimum v cc requirement of the ats636lse. the small capaci- tor on the output of the device improves the emc performance of the device. the pull-up resistor should be chosen to limit the current through the output transistor; do not exceed the maximum continuous output current of the device. note: this circuit cannot be used to program the device, as the series resistance is too large, and a minimum capacitance of 0.1 f must be connected from vcc to gnd of the sip to pro- vide the current necessary to blow the fuse. extensive applications information on magnets and hall- effect ics including chopper stabilization is available in the allegro electronic data book cd, or at the website: http://www.allegromicro.com. 1.2k ohm v supply vcc 1 r l 100 ohm 2 4 gnd r s 0.1 f 5v vout ats636 120 pf typical application: typical application circuit
programmable back biased hall-effect switch with tpos functionality 13 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com ats636lse power derating ? se package due to internal power consumption, the junction temperature of the ic (junction temperature, t j ) is higher than the ambient environment temperature, t a . to ensure that the device does not operate above the maximum rated junction temperature use the following calculations: t = p d r ja where: p d = v cc i cc t = v cc i cc r ja where t denotes the temperature rise resulting from the ic?s power dissipation. t j = t a + t r ja = 77c/w t j (max) = 165c typical t j calculation: t a = 25c v cc = 5 v i cc(on) = 5.5 ma p d = v cc i cc = 5 v 5.5 ma = 27.5 mw t = p d r ja = 27.5 mw 77c/w = 2.0c t j = t a + t = 25c + 2.0c = 27.0c maximum allowable power dissipation calculation: t j = t a + t t j (max) = 165c, if t a = 150c then: 165 = 150 + t t = 15c t = p d r ja (r ja = 77c/w) \ p d (max) = 15c / 77c/w = 195 mw at t a = 150c maximum v cc for p d (max) = 111 mw at t a = 150c p d = v cc i cc , i cc = 10 ma (max) at 150c v cc = p d / i cc = 195 mw / 5.5 ma = 35.4 v 0 500 1000 1500 2000 2500 3000 3500 4000 4500 20 40 60 80 100 120 140 160 180 temperature (c) power dissipation, p d (m w) power dissipation versus ambient temperature (r q ja = 77 oc/w) 2-layer pcb
programmable back biased hall-effect switch with tpos functionality 14 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com ats636lse package se 4-pin sip 1.0 ref 0.90.1 1.30.1 4.90.1 3.30.1 10.000.05 7.000.05 6.230.10 11.600.10 0.600.10 24.650.10 0.71 0.10 0.71 0.10 1.60 0.10 1.270.10 5.50 0.10 2.000.10 1.0 ref for reference only, not for tooling use (reference dwg-9001) dimensions in millimeters 24 3 1 a a a b c c d d b dambar removal protrusion (16x) metallic protrusion, electrically connected to pin 4 and substrate (both sides) thermoplastic molded lead bar for alignment during shipment standard branding reference view lllllll yyww nnn branded face = supplier emblem l = lot identifier n = last three numbers of device part number y = last two digits of year of manufacture w = week of manufacture branding scale and appearance at supplier discretion 0.38 +0.06 ?0.04 e e f f active area depth, 0.43 mm hall element (not to scale)
programmable back biased hall-effect switch with tpos functionality 15 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com ats636lse for the latest version of this document, visit our website: www.allegromicro.com copyright ?2005-2012, allegro microsystems, inc. allegro microsystems, inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. revision history revision revision date description of revision rev. 5 january 30, 2012 update product availability

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